The present invention generally relates to semiconductor memory devices and methods of producing the same, and more particularly to a thin film transistor (TFT) load type static random access memory (SRAM) and a method of producing such a TFT load type SRAM.
Up to now, the high resistance load type SRAM was popularly used. However, as the integration density improves and the number of memory cells increases, the current consumption increases and various problems are generated. In order to avoid such problems and the help of the progress in the semiconductor technology, the SRAM having the TFT load has been realized. However, new problems are generated due to the use of the TFT load, and it is necessary to eliminate these new problems.
An example of a conventional method of producing the high resistance load type SRAM will be described with reference to FIGS.1A through 1J and FIGS. 2A through 2F. FIGS. 1A through 1J are side views in cross section showing essential parts of the high resistance load type SRAM at essential stages of the conventional method of producing the high resistance load type SRAM. FIGS. 2A through 2F are plan views of the high resistance load type SRAM at essential stages of the conventional method of producing the high resistance load type SRAM. FIGS.1A through 1J respectively are cross sections taken along a line which corresponds to a line Y--Y in the plan view of FIG.2F.
In FIG.1A, a silicon dioxide (SiO.sub.2) layer is used as a pad layer, for example, and a silicon nitride (Si.sub.3 N.sub.4) layer which is formed on the SiO.sub.2 layer is used as an oxidation resistant mask layer when carrying out a selective thermal oxidation (for example, a local oxidation of silicon (LOCOS)) so as to form a field insulator layer 2 on a silicon (Si) semiconductor substrate 1. This field insulator layer 2 is made of SiO.sub.2 and has a thickness of 4000 .ANG., for example.
Then, the Si.sub.3 N.sub.4 layer and the SiO.sub.2 layer which are used when carrying out the selective thermal oxidation are removed to expose an active region of the Si semiconductor substrate 1.
In FIG.1B, a thermal oxidation is carried out to form a gate insulator layer 3 which is made of SiO.sub.2 and has a thickness of 100 .ANG., for example.
By carrying out a resist process of the photolithography technique and a wet etching using hydrofluoric acid as the etchant, the gate insulator layer 3 is selectively etched to form a contact hole 3A.
In FIGS.1C and 2A, a chemical vapor deposition (CVD) is carried out to form a first polysilicon layer having a thickness of 1500 .ANG., for example.
Then, a vapor phase diffusion is carried out to introduce phosphorus (P) of 1.times.10.sup.20 cm.sup.-3, for example, so as to form an n.sup.+ -type impurity region 5'.
In FIG.2A, the illustration of the first polysilicon layer is omitted for the sake of convenience.
In FIG.1D, a resist process of the photolithography technique and a reactive ion etching (RIE) using CCl.sub.4 /O.sub.2 as the etching gas are carried out to pattern the first polysilicon layer and form a gate electrode 4. The gate electrode 4 becomes the gate electrode of a word line and a driver transistor.
An ion implantation is carried out to inject As ions with a dosage of 3.times.10.sup.15 cm.sup.-2 and an acceleration energy of 40 keV, so as to form a source region 5 and a drain region 6.
In FIGS.1E and 2B, a CVD is carried out to form an insulator layer 7 which is made of SiO.sub.2 and has a thickness of 1000 .ANG., for example.
By carrying out a resist process of the photolithography technique and a RIE using CHF.sub.3 /He as the etching gas, a ground line contact hole 7A is formed. This ground line contact hole 7A cannot be seen in FIG.1E.
In FIG.1F, a CVD is carried out to form a second polysilicon layer having a thickness of 1500 .ANG., for example.
Then, an ion implantation is carried out to inject P ions into the second polysilicon layer with a dosage of 4.times.10.sup.15 cm.sup.-2 and an acceleration energy of 30 keV, and an annealing is carried out to reduce the resistance.
A resist process of the photolithography technique and a RIE using CCl.sub.4 /O.sub.2 as the etching gas are carried out to pattern the second polysilicon layer and form a ground line 8.
In FIGS.1G and 2C, a CVD is carried out to form an insulator layer 9 which is made of SiO.sub.2 and has a thickness of 1000 .ANG., for example.
A resist process of the photolithography technique and a RIE using CHF.sub.3 /He as the etching gas are carried out to selectively etch the insulator layers 9 and 7 and form a load resistor contact hole 9A.
In FIG.1H, a CVD is carried out to form a third polysilicon layer having a thickness of 1500 .ANG., for example.
A resist process of the photolithography technique and an ion implantation with a dosage of 1.times.10.sup.15 cm.sup.-2 and an acceleration energy of 30 keV are carried out to inject As ions into a part where a supply line of a positive power source voltage Vcc is formed and a part where the high resistance load makes contact with the gate electrode 4.
By carrying out a resist process of the photolithography technique and a RIE using CCl.sub.4 /O.sub.2 as the etching gas, the third polysilicon layer is patterned to form a contact part 10, a high resistance load 11 and a Vcc supply line 12.
In FIGS.1I and 2D, a CVD is carried out to form an insulator layer which is made of SiO.sub.2 and has a thickness of 1000 .ANG., for example, and an insulator layer which is made of phosphosilicate glass (PSG) and has a thickness of 5000 .ANG., for example. In FIG.1I, these insulator layers are referred to as an insulator layer 13.
A thermal process is thereafter carried out to reflow and planarize the insulator layer 13.
Next, a resist process of the photolithography technique and a RIE using CHF.sub.3 /He as the etching gas are carried out to selectively etch the insulator layer 13 and the like and to form a bit line contact hole 13A.
In FIGS.1J and 2E, a sputtering is carried out to form an aluminum (A1) layer having a thickness of 1 .mu.m, for example. This A1 layer is patterned using the normal photolithography technique so as to form a bit line 14. Those elements which are shown in FIGS.1J and 2E but not yet described, such as "BL", will be readily understood from the description given later in conjunction with FIG.3.
FIG.2F shows the plan view of the essential part of the high resistance load type SRAM which is completed by the above described processes. In FIG.2F, those parts which are the same as those corresponding parts in FIGS.1A through 1J and FIGS.2A through 2E are designated by the same reference numerals. However, for the sake of convenience, the illustration of the A1 bit line 14 shown in FIGS.1J and 2E is omitted in FIG.2F.
FIG.3 shows an equivalent circuit diagram of the essential part of the high resistance load type SRAM described above in conjunction with FIGS.1A through 1J and 2A through 2F.
FIG.3 shows driver transistors Q1 and Q2, transfer gate transistors Q3 and Q4, high resistance loads R1 and R2, a word line WL, bit lines BL and BL, nodes S1 and S2, the positive power source voltage Vcc, and a negative power source voltage Vss.
The operation of this high resistance load type SRAM, the storage operation in particular, is carried out as follows.
If it is assumed that the positive power source voltage Vcc is 5 V, the negative power source voltage Vss is 0 V, the node S1 is 5 V and the node S2 is 0V, the transistor Q2 is ON and the transistor Q1 is OFF. The potential at the node S1 is maintained to 5 V if the transistor Q1 is OFF and the resistance is sufficiently high compared to the high resistance load R1. The potential at the node S2 is maintained to 0 V if the transistor Q2 is ON and the resistance is sufficiently low compared to the high resistance load R2.
However, under the above described condition, a D.C. current flows from the positive power source voltage Vcc supply line to the negative power source voltage Vss supply line via the node S2, and the current value is inversely proportional to the value of the high resistance load R2.
When the integration density of the above described high resistance load type SRAM increases, the number of memory cells per chip increases and the current consumption of the entire chip would become very large if the current consumption per memory is not reduced. Hence, the D.C. current described above must be reduced, but in order to reduce this D.C. current, the values of the high resistance loads R1 and R2 must be set large. However, when the values of the high resistance loads R1 and R2 are set large, it becomes difficult to stably maintain the potential at the nod having the driver transistor which is OFF, that is, the potential at the node S1 in FIG.3.
Because of the above described background, the TFT load type SRAM which uses the TFT as the load in place of the high resistance load has been developed.
Next, a description will be given of the TFT load type SRAM. Similarly to the description given above in respect of the high resistance load type SRAM, a description will first be given of the method of producing the TFT load type SRAM.
An example of a conventional method of producing the TFT load type SRAM will be described with reference to FIGS.4A through 4D and FIGS.5A through 5D. FIGS.4A through 4D are side views in cross section showing essential parts of the TFT load type SRAM at essential stages of the conventional method of producing the high resistance load type SRAM. FIGS.5A through 5D are plan views of the TFT load type SRAM at essential stages of the conventional method of producing the TFT load type SRAM. FIGS.4A through 4D respectively are cross sections taken along a line which corresponds to a line Y--Y in the plan view of FIG.5D.
The processes of producing the TFT load type SRAM at the beginning are basically the same as the processes described in conjunction with FIGS.1A through 1G up to the process of forming the load resistor contact hole 9A of the high resistance load type SRAM, and a description thereof will be omitted. The only difference is that a contact hole 8A shown in FIG.5A is formed with respect to the ground line 8 which is made of the second polysilicon layer, so that a gate electrode of a TFT which is formed by a third polysilicon layer can make contact with an active region and the gate electrode 4 which is formed by the first polysilicon layer. Hence, a description will only be given from the processes thereafter. In FIGS.4A through 4D and 5A through 5D, those parts which are the same as those corresponding parts in FIGS.1A through 1J and 2A through 2F are designated by the same reference numerals.
In FIGS.4A and 5A, a CVD is carried out to form a third polysilicon layer having a thickness of 1500 .ANG., for example.
Then, an ion implantation is carried out to inject P ions with a dosage of 4.times.10.sup.15 cm.sup.-2 and an acceleration energy of 30 keV.
Further, a resist process of the photolithography technique and a RIE using CCl.sub.4 /O.sub.2 as the etching gas are carried out to pattern the third polysilicon layer and form a gate electrode 15 of the TFT.
In FIG.4B, a CVD is carried out to form a gate insulator layer 16 of the TFT, which is made of SiO.sub.2 and has a thickness of 300 .ANG., for example.
A resist process of the photolithography technique and a wet etching using hydrofluoric acid as the etchant are carried out to selectively etch the gate insulator layer 16 and form a drain contact hole 16A.
In FIGS.4C and 5B, a CVD is carried out to form a fourth polysilicon layer having a thickness of 500 .ANG., for example.
A resist process of the photolithography technique and an ion implantation with a dosage of 1.times.10.sup.14 cm.sup.-2 and an acceleration energy of 5 keV are carried out to inject B ions into a part where a supply line of a positive power source voltage Vcc is made and into a part where the TFT source and drain regions are formed.
A resist process of the photolithography technique and a RIE using CCl.sub.4 /O.sub.2 as the etching gas are carried out to pattern the fourth polysilicon layer and form a source region 17, a drain region 18 and a channel region 19 of the TFT and also form a Vcc supply line 20.
In FIGS.4D and 5C, a CVD is carried out to form an insulator layer made of SiO.sub.2 and having a thickness of 1000 .ANG., for example, and an insulator layer made of PSG and having a thickness of 5000 .ANG., for example. In FIG.4D, these two insulator layers are shown as one insulator layer 21, similarly as in the case of FIGS.1I and 1J.
Then, a thermal process is carried out to reflow and planarize the insulator layer 21.
Next, a resist process of the photolithography technique and a RIE using CHF.sub.3 /He as the etching gas are carried out to selectively etch the insulator layer 21 and the like and to form a bit line contact hole.
A sputtering is carried out thereafter to form an A1 layer having a thickness of 1 .mu.m, for example, and this A1 layer is patterned by the normal photolithography technique to form a bit line 22. Those elements which are shown in FIGS.4D and 5C but not yet described, such as "BL", will be readily understood from the description given later in conjunction with FIG.6.
FIG.5D shows the plan view of the essential part of the TFT load type SRAM which is completed by the above described processes. In FIG.5D, those parts which are the same as those corresponding parts in FIGS.4A through 4D and FIGS.5A through 5D are designated by the same reference numerals. However, for the sake of convenience, the illustration of the A1 bit line 22 shown in FIGS.4D and 5C is omitted in FIG.5D.
FIG.6 shows an equivalent circuit diagram of an essential part of the TFT load type SRAM described in conjunction with FIGS.4A through 4D and 5A through 5D. In FIG.6, those parts which are the same as those corresponding parts in FIGS.4A through 4D and 5A through 5D are designated by the same reference numerals.
FIG.6 shows transistors Q5 and Q6 which are load TFTs used in place of the high resistance loads R1 and R2 shown in FIG.3.
Next, a description will be given of the operation of the TFT load type SRAM, and the storing operation in particular.
If it is assumed that the positive power source voltage Vcc is 5 V, the negative power source voltage Vss is 0 V, the node S1 is 5 V and the node S2 is 0 V, the transistor Q6 is OFF when the transistor Q2 is ON and the transistor Q5 is ON when the transistor Q1 is OFF. The potential at the node S1 is maintained to 5 V if the transistor Q1 is OFF and the resistance is sufficiently high compared to the transistor Q5 which is ON. The potential at the node S2 is maintained to 0 V if the transistor Q2 is ON and the resistance is sufficiently small compared to the transistor Q6 which is ON.
Under the above described condition, the resistance of the load transistor Q5 or Q6 changes depending on the stored information, and thus, the problems of the high resistance load type SRAM is eliminated. That is, it is possible to carry out a stable information storage operation. The channels of the transistors Q5 and Q6, that is, the channels of the load TFTs, are made of polysilicon. The crystal state of the polysilicon which forms the channels is considerably poor compared to the single crystal, and a current easily leaks even when the transistor is OFF. Such a leak current increases the current consumption of the chip, and it is desirable to make the channel as small as possible.
On the other hand, as may be readily seen from FIG.4D, the bit line 22 which is made of the A1 layer is provided at the top layer of the TFT load type SRAM. In addition, the channel of the load TFT exists immediately under the bit line 22 via the insulator layer 21 which is made of PSG or the like.
But according to this construction, the bit line 22 which is made of the A1 layer can be regarded as a gate electrode of a transistor, and the underlying insulator layer 21 can be regarded as a gate insulator layer of this transistor. In addition, the potential of the bit line 22 which is regarded as the gate electrode varies between 0 v (Vss) and 5 V (Vcc). As a result, the TFT which should be OFF, that is, the transistor Q6 becomes nearly ON, and the leak current increases and the parasitic effect becomes notable.
Accordingly, a double gate structure TFT load type SRAM was developed in order to eliminate the above described problems of the TFT load type SRAM.
According to the double gate structure TFT load type SRAM, the above described problems of the TFT load type SRAM are eliminated by interposing the third polysilicon layer of the TFT load type SRAM described in conjunction with FIGS.4 through 6 between the fourth polysilicon layer and the bit line 22 which is made of A1. Particularly, a fifth polysilicon layer forming a second gate electrode which has the same pattern as the gate electrode 15 of the TFT is interposed between the A1 bit line 22 and the fourth polysilicon layer which forms the source region 17, the drain region 18, the channel region 19, the Vcc supply line 20 and the like.
FIGS.7A through 7C are side views in cross section showing essential parts of the double gate structure TFT load type SRAM at essential stages of the conventional method of producing the double gate structure TFT load type SRAM. The processes of producing the double gate structure TFT load type SRAM at the beginning are basically the same as the processes described in conjunction with FIGS.4A through 4C up to the process of forming the source region 17, the drain region 18, the channel region 19 and the Vcc supply line 20 of the TFT load type SRAM, and a description thereof will be omitted. Hence, a description will only be given from the processes thereafter. In FIGS.7A through 7C, those parts which are the same as those corresponding parts in FIGS.1 through 6 are designated by the same reference numerals.
In FIG.7A, a CVD is carried out to form an insulator layer 23 which is made of SiO.sub.2 and has a thickness of 500 .ANG., for example.
A resist process of the photolithography technique and a RIE using CHF.sub.3 +He as the etching gas are carried out to selectively etch the insulator layer 23 and to form a contact hole 23A with respect to the drain electrode 18 of the TFT.
In FIG.7B, a CVD is carried out to form a fifth polysilicon layer having a thickness of 1000 .ANG., for example.
Then, an ion implantation is carried out to inject P ions into the fifth polysilicon layer with a dosage of 4.times.10.sup.15 cm.sup.-2, for example.
A resist process of the photolithography technique and a RIE using CCl.sub.4 /O.sub.2 as the etching gas are carried out to pattern the fifth polysilicon layer and to form a second gate electrode 24 of the TFT.
In FIG.7C, a CVD is carried out to form an insulator layer which is made of SiO.sub.2 and has a thickness of 1000 .ANG., for example, and an insulator layer which is made of PSG and has a thickness of 5000 .ANG., for example. As in the case shown in FIG.4D, these two insulator layers are shown as one insulator layer 25 in FIG.7C.
Thereafter, a thermal process is carried out to reflow and planarize the insulator layer 25.
Next, a resist process of the photolithography technique and a RIE using CHF.sub.3 /He as the etching gas are carried out to selectively etch the insulator layer 25 and the like, and to form a bit line contact hole.
In addition, a sputtering is carried out to form an A1 layer having a thickness of 1 .mu.m, for example, and this A1 layer is patterned by the normal photolithography technique so as to form a bit line 26.
As described heretofore, the SRAM started from the high resistance load type, evolved to the TFT load type, and further evolved to the double gate structure TFT load type. However, as may be seen by comparing FIGS.1A through 1J with FIGS.7A through 7C, and FIGS.1J and 7C in particular, the number of polysilicon layers has increased by two from the high resistance load type SRAM to the double gate structure TFT load type SRAM, and the number of mask processes have increased by four.